The present disclosure relates generally to delay locked loop (DLL) circuits. More particularly, this disclosure relates to a DLL circuit which is based on a variable length plurality of differential delay elements, an advanced common biasing technique which tolerates process variations and calibrates current ranges for operational variances and lock detection for faster processing.
Delay-locked loops are often used in the I/O interfaces of digital integrated circuits in order to hide clock distribution delays and to improve overall system timing. In recent years, the demand has risen for devices capable of high-speed processing. As a result, the demand for DLL circuits that quickly compensate for electronic noise and capacitive delays has also risen.
One type of design used by those skilled in the art to minimize the noise present in the circuit at the required speed is a self-bias signal technique. Referring to FIG. 1, this prior art DLL circuit is a self-biasing configuration that is composed of a phase comparator, charge pump, loop filter, bias generator and a plurality of delay cells. In this configuration, devices dependent on a precisely delayed clock signal must delay processing for a standardized time period to insure that the received signal is exact. This processing delay is caused by the fact that most DLL circuits are designed to tolerate the worst-case conditions. The DLL circuit performance during this worst-case condition is the processing delay time set for most devices using the output of this circuit.
This prior art design uses a constant charge pump current which gives rise to a constant damping factor and a constant loop bandwidth. A constant bandwidth can constrain the achievement of a wide operating frequency range and low input tracking jitter. If the frequency is disturbed, the phase error that results from each cycle of the disturbance will accumulate for many cycles until the loop can compensate for the phase error. The error will be accumulated for a number of cycles, which is proportional to the operating frequency divided by the loop bandwidth. Thus the loop bandwidth would have to be positioned as close as possible to the reference frequency bandwidth to minimize the total phase error. The result is that the frequency bandwidth must be conservatively set for stability at the lowest operating frequency with worst case process variations rather than set for optimized jitter performance. The self-biased DLL also exhibits much faster locking times only when locking from similar or higher operating frequencies. However, if the self-biased DLL is started at a very low operating frequency, it will exhibit very slow locking times.
Accordingly, there is a need for a DLL circuit which provides a fast lock-up circuit, has better jitter performance, tolerates process variations, reduces power consumption, reduces processing delay time and extends the DLL operating frequency range.
The use of the same reference symbols in different drawings indicates similar or identical items.